A high level modeling system (HLMS) is a computer-based circuit design tool that allows a user to create a circuit design at a high level of abstraction. An HLMS provides a graphic design environment within which the user creates circuit designs using a “drag-and-drop” design paradigm. The user can drag graphic blocks into the design environment. Each graphic block represents a particular circuit function. For example, a graphic block can represent a function such as multiplexing, addition, multiplication, filtering, or the like. Within the design environment, the user also can specify connectivity and signal flows within the circuit design and among the blocks by drawing lines representing signals that interconnect the various blocks within the design environment of the HLMS.
Because the circuit design is specified at a high level of abstraction, significant processing is required in order to express the HLMS circuit design as a low level circuit design, e.g., using a hardware description language such as VHDL or Verilog or in the form of a netlist. Examples of some of the process steps can include flattening the hierarchically ordered HLMS circuit design, scrubbing names of particular blocks and signals, etc. The HLMS performs these processing steps to avoid conflicts between names and to avoid other syntactic issues when the HLMS circuit design, which is typically a subsystem of a larger system design, is joined with other subsystems of the larger system design. This processing, however, makes it difficult for a user to identify the low level circuit components generated, or derived from, the blocks, signals, and ports of the HLMS circuit design.
Presently, users have a limited ability to specify constraints within an HLMS circuit design. Typically, constraints may only be applied to the boundary of the HLMS circuit design, but not to internal nodes of the HLMS circuit design. This means that the user must manually apply low level design constraints to the low level circuit design generated from the HLMS circuit design. Unfortunately, the processing that generates the low level circuit design, as noted, makes it difficult for a user to identify the correct low level circuit components to which constraints are to apply.